This invention relates to the field of the fabrication of integrated circuits. In particular, this invention relates to determining a layout for wide wire on-chip interconnect lines.
Development of integrated circuits continues to push the boundaries of miniaturization. On-chip devices are becoming smaller and more numerous which boosts performance but increases the difficulty of wiring them together. The conductivity of the metal used to interconnect the devices is increasingly important. The most commonly used material for metal interconnect lines up to several years ago has been aluminium. However, aluminium imposes limitations on minimal wire width due to high vulnerability to electromigration (the process by which a metal conductor changes shape under the influence of an electric current flowing through it and which eventually leads to the breaking of the conductor). Other metals suitable for use in interconnect lines have therefore been sought.
Copper has a significantly better resistance to electromigration than aluminium, therefore, chips using copper interconnect can have smaller metal components. In addition to this, copper is a better conductor than aluminium, so copper wires use less energy to pass electricity through them. Together, these effects lead to higher-performance processors. Copper-based processors continue to be the state of the art for the semiconductor industry today.
The relative transition from aluminium to copper required significant developments in fabrication techniques, namely, introducing the “Damascene” (or “dual-Damascene”) process whose crucial stage is chemical-mechanical polishing (CMP). Applying CMP to the region of wide wires leads to excessive removal of copper (“dishing”), while in the region of large areas of dielectric excessive dielectric layer is left.
In order to prevent these unwanted effects, the percentage of copper within any area of a given size on an integrated circuit must fall within a predefined limit. This is called the copper density Physical Design Rule which is a part of Technology Physical Design Rules issued by process technology vendors per technology. For example, the copper density may be required to be within 15% and 85%. The density may be checked automatically for every 50 μm square area of an integrated circuit design. In addition to this, in order to reduce the damage caused by dishing of copper wires, the Design Rules limit maximal width of such wires.
During the design process of an integrated circuit the layout is designed using computer aided design with software tools for performing various tasks aiding the designer. Technology Physical Design Rules always include a section which defines ranges of acceptable dimensions of interconnects for given technologies. These Physical Design Rules must be adhered to, and Design Rules Check (DRC) is a computer program product that checks design compliance with the Physical Design Rules. DRC is an indispensable part of computer aided design packages.
One or more interconnect lines may be identified as critical in a given design, and while embodiments might be envisaged where all interconnect lines are treated as critical, typically only a small subset of interconnect lines in a design are critical. Critical interconnect lines can be modelled as transmission lines (also referred to as T-lines).
Transmission lines have a special geometry in that as well as lines carrying signals they have shielding lines which return current. The shielding lines may be at the side of the signal line such that the transmission line can consist of a single metal layer (coplanar waveguides) or at the bottom such that the signal line can be shielded from a lossy substrate below by means of a ground shield (microstrip lines). Both signal and ground layers can be routed using copper metal layers.
Transmission lines are implemented as electronic devices in an integrated circuit in that they have a parametric structure which can be varied by the designer according to design needs and dimensions. They can be provided as an off-the-shelf device which can be inserted into a design. On one hand, they should comply with Technology Physical Design Rules. On the other hand, in order to guarantee sufficiently low losses in critical interconnect, both signal and shielding lines should be wide, usually wider than maximum width allowed by Design Rules. The present invention suggests a solution to this contradiction.